The present invention relates to an operation of a non-volatile memory device. More particularly, the present invention relates to a method of operating a flash memory device in which bit lines to which an inhibited cell is connected are boosted sufficiently.
Semiconductor memory devices can be classified into volatile memory devices that lose data as time goes by, such as dynamic random access memory (DRAM) and static random access memory (SRAM), and non-volatile memory devices that can retain its data.
There is an increasing demand for flash memory to/from which data can be input/output electrically. Flash memory is a device in which the data can be electrically erased at high speed in a state where circuits are not removed from a board. Flash memory has a simple memory cell structure and is therefore advantageous in that the production prime cost per unit memory is cheap. Flash memory is also advantageous in that it does not require a refresh function for retaining data.
Flash memory is largely classified into a NOR type and a NAND type. NOR type flash memory requires one contact per two cells and is disadvantageous in high integration, but is advantageous in high speed due to a high cell current. NAND type flash memory is disadvantageous in high speed due to a low cell current, but is advantageous in high integration since a plurality of contacts shares one contact. Accordingly, the NAND flash memory devices have been in the spotlight as the next-generation memory devices in the use of digital devices, such as MP3, digital camera, mobile and auxiliary storage devices, increases rapidly.
FIG. 1 is a view illustrating the unit string of a NAND flash memory device.
Referring to FIG. 1, the unit string of the NAND flash memory device includes a gate in which a floating gate 110 and a control gate 120 are stacked between a drain select transistor DST for selecting a unit string and a source select transistor SST for selecting ground. Memory cells MC0 through MC31, having the gate, are connected in series, thus constituting one string.
The string is connected to a bit line BL (not shown). A plurality of structures in each of which the string and the bit line are connected is connected in parallel to thereby form one block. The blocks are symmetrically arranged on the basis of a bit line contact. The select transistors DST (not shown), SST (not shown) and the memory cells MC0 through MC31 are arranged in a matrix form of rows and columns. The gates of the drain select transistor DST and the source select transistor SST arranged in the same column are connected to a drain select line DSL and a source select line SSL, respectively. The gates of the memory cells MC0 through MC31 arranged in the same column are connected to a plurality of corresponding word lines WL0 through WL31. Further, the drain of the drain select transistor DST is connected to the bit line BL and to the source of the source select transistor SST is connected a common source line CSL (not shown).
A program operation of the NAND flash memory device as constructed above is described below.
Programming is performed by injecting electrons of a channel area into a floating gate by Fowler-Nordheim (F-N) tunneling, which is generated due to a high voltage difference, between a channel area and a control gate of a selected memory cell, as 0V is applied to a selected bit line and a program voltage Vpgm is applied to a selected word line.
However, the program voltage Vpgm is applied not only to a selected memory cell, but also to unselected memory cells that are arranged along the same word line, so that the unselected memory cells connected to the same word line are also programmed. This phenomenon is called program disturbance. In order to prevent such program disturbance, after the source of the drain select transistor DST of a string, including unselected memory cells connected to a selected word line and unselected bit lines, is precharged to a level Vcc−Vth (Vcc is power source voltage and Vth is the threshold voltage of the drain select transistor), the selected word line is applied with the program voltage Vpgm and unselected word lines are applied with a pass voltage Vpass, so that a channel voltage Vch of the memory cells belonging to the same string, is boosted.
In the method of boosting the channel voltage in order to inhibit unselected memory cells from being programmed, the degree of boosting can vary depending on how program cells are arranged around a selected word line. Further, disturbance can occur since boosting is insufficient.